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DISCRETE SEMICONDUCTORS
DATA SHEET
BF1101; BF1101R; BF1101WR N-channel dual-gate MOS-FETs
Product specification Supersedes data of 1999 Feb 01 1999 May 14
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
FEATURES * Short channel transistor with high forward transfer admittance to input capacitance ratio * Low noise gain controlled amplifier up to 1 GHz * Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. APPLICATIONS * VHF and UHF applications with 3 to 7 V supply voltage, such as television tuners and professional communications equipment.
handbook, 2 columns 4
BF1101; BF1101R; BF1101WR
PINNING PIN 1 2 3 4 DESCRIPTION source drain gate 2 gate 1
Top view
MSB035
handbook, 2 columns 3
4
2
1
BF1101R marking code: NCp.
Fig.2
Simplified outline (SOT143R).
3
fpage
3
4
DESCRIPTION Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1101, BF1101R and BF1101WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively.
1 Top view 2
MSB014
2 Top view
1
MSB842
BF1101 marking code: NDp.
BF1101WR marking code: NC.
Fig.1
Simplified outline (SOT143B).
Fig.3
Simplified outline (SOT343R).
QUICK REFERENCE DATA SYMBOL VDS ID Ptot yfs Cig1-ss Crss F Xmod Tj PARAMETER drain-source voltage drain current total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure cross-modulation operating junction temperature CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. 1999 May 14 2 f = 1 MHz f = 800 MHz input level for k = 1% at 40 dB AGC CONDITIONS - - - 25 - - - 100 - MIN. - - - 30 2.2 25 1.7 - - TYP. 7 30 200 - 2.7 35 2.5 - 150 MAX. UNIT V mA mW mS pF fF dB dBV C
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS ID IG1 IG2 Ptot Tstg Tj Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER thermal resistance from junction to soldering point PARAMETER drain-source voltage drain current gate 1 current gate 2 current total power dissipation storage temperature operating junction temperature Ts 110 C; note 1
BF1101; BF1101R; BF1101WR
CONDITIONS - - - - -
MIN. 7
MAX. V 30 10 10 200 +150 +150
UNIT mA mA mA mW C C
-65 -
VALUE 200
UNIT K/W
MGL615
handbook, halfpage
250
Ptot (mW)
200
150
100
50
0 0 50 100 150 Ts (C) 200
Fig.4 Power derating curve.
1999 May 14
3
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
STATIC CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL V(BR)DSS PARAMETER drain-source breakdown voltage
BF1101; BF1101R; BF1101WR
CONDITIONS VG1-S = VG2-S = 0; ID = 10 A VG2-S = VDS = 0; IG1-S = 10 mA VG1-S = VDS = 0; IG2-S = 10 mA VG2-S = VDS = 0; IS-G1 = 10 mA VG1-S = VDS = 0; IS-G2 = 10 mA VG2-S = 4 V; VDS = 5 V; ID = 100 A VG1-S = 5 V; VDS = 5 V; ID = 100 A VG2-S = 4 V; VDS = 5 V; RG1 = 120 k; note 1 VG2-S = VDS = 0; VG1-S = 5 V VG1-S = VDS = 0; VG2-S = 4 V
MIN. 7 7 7 0.5 0.5 0.3 0.3 8 - -
MAX. - 16 16 1.5 1.5 1.0 1.2 16 50 20
UNIT V V V V V V V mA nA nA
V(BR)G1-SS gate 1-source breakdown voltage V(BR)G2-SS gate 2-source breakdown voltage V(F)S-G1 V(F)S-G2 VG1-S (th) VG2-S (th) IDSX IG1-SS IG2-SS Note 1. RG1 connects G1 to VGG = 5 V; see Fig.21. forward source-gate 1 voltage forward source-gate 2 voltage gate 1-source threshold voltage gate 2-source threshold voltage drain-source current gate 1 cut-off current gate 2 cut-off current
DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified. SYMBOL yfs Cig1-ss Cig2-ss Coss Crss F Xmod PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance noise figure cross-modulation f = 1 MHz f = 1 MHz f = 1 MHz f = 800 MHz; YS = YS opt input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; note 1 input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; note 1 Note 1. Measured in test circuit of Fig.21. CONDITIONS pulsed; Tj = 25 C MIN. 25 - - - - - 85 100 TYP. 30 2.2 1.6 1.2 25 1.7 - - MAX. 40 2.7 - - 35 2.5 - - UNIT mS pF pF pF fF dB dBV dBV
reverse transfer capacitance f = 1 MHz
1999 May 14
4
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1101; BF1101R; BF1101WR
MGS299
MGS300
handbook, halfpage
20
ID (mA) 16
VG2-S = 4 V 3.5 V
3V
handbook, halfpage
20
ID (mA) 16
VG1-S = 1.6 V
2.5 V
1.5 V 12 2V 8 8 12 1.4 V 1.3 V 1.2 V 4 1.5 V 4 1.1 V 1V 1V 0 0 0.4 0.8 1.2 1.6 VG1-S (V) 2 0 0 2 4 6 VDS (V) 8
VDS = 5 V. Tj = 25 C.
VG2-S = 4 V. Tj = 25 C.
Fig.5 Transfer characteristics; typical values.
Fig.6 Output characteristics; typical values.
MGS301
handbook, halfpage
100
I G1 (A) 80
VG2-S = 4 V 3.5 V 3V
handbook, halfpage
40
MGS302
y fs (mS) 30
VG2-S = 4 V 3.5 V 3V
60 2.5 V 40 2V 20 2.5 V 10 20
0 0 0.5 1 1.5 2 VG1-S (V) 2.5
0 0 4 8 12
2V 16 20 I D (mA)
VDS = 5 V. Tj = 25 C.
VDS = 5 V. Tj = 25 C.
Fig.7
Gate 1 current as a function of gate 1 voltage; typical values.
Fig.8
Forward transfer admittance as a function of drain current; typical values.
1999 May 14
5
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1101; BF1101R; BF1101WR
MGS303
handbook, halfpage
20
handbook, halfpage
15
MGS304
ID (mA) 16
ID (mA) 10
12
8 5 4
0 0 10 20 30 40 50 I G1 (A)
0 0 1 2 3 4 5 VGG (V)
VDS = 5 V. VG2-S = 4 V. Tj = 25 C.
VDS = 5 V; VG2-S = 4 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.21.
Fig.9
Drain current as a function of gate 1 current; typical values.
Fig.10 Drain current as a function of gate 1 supply voltage (= VGG); typical values.
MGS305
handbook, halfpage
20
ID (mA) 16
R G1 = 47 k 68 k
82 k 100 k 120 k 150 k
handbook, halfpage
16
MGS306
ID (mA) 12
VGG = 5 V 4.5 V 4V 3.5 V 3V
12
180 k 220 k 8
8 4 4
0 0 2 4 6 VGG = VDS (V) 8
0 0 2 4 VG2-S (V) 6
VG2-S = 4 V; Tj = 25 C. RG1 connected to VGG; see Fig.21.
VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.21.
Fig.11 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values.
Fig.12 Drain current as a function of gate 2 voltage; typical values.
1999 May 14
6
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1101; BF1101R; BF1101WR
handbook, halfpage
40
MGS307
MGS308
handbook, halfpage
(3) (2) (1)
I G1 (A) 30 VGG = 5 V 4.5 V 4V 20 3.5 V 3V 10
0 gain reduction (dB) -10
-20
-30
-40
0 0 2 4 VG2-S (V) 6
-50
0
1
2
3
VAGC (V)
4
VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.21.
VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb = 25 C. (1) RG1 = 68 k. (2) RG1 = 120 k. (3) RG1 = 180 k.
Fig.13 Gate 1 current as a function of gate 2 voltage; typical values.
Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21.
MGS309
MGS310
handbook, halfpage
120
handbook, halfpage
25
Vunw (dBV) 110
ID (mA)
20
(1)
15
(2)
100
(1) (2)
(3)
10
(3)
90 5
80 0 10 20 30 40 50 gain reduction (dB)
0 0 10 20 30 40 50 gain reduction (dB)
VDS = 5 V; VGG = 5 V; f = 50 MHz; funw = 60 MHz; Tamb = 25 C. (1) RG1 = 68 k. (2) RG1 = 120 k. (3) RG1 = 180 k.
VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb = 25 C. (1) RG1 = 68 k. (2) RG1 = 120 k. (3) RG1 = 180 k.
Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.21.
Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21.
1999 May 14
7
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1101; BF1101R; BF1101WR
102 handbook, halfpage yis (mS)
MGS311
102 handbook, halfpage |yrs | (mS)
MGS312
rs
-102 rs (deg)
10
|yrs|
10 bis 1
-10
g is 10 -1 10 1 10 -1 103
102
f (MHz)
103
102
f (MHz)
VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C.
Fig.17 Input admittance as a function of frequency; typical values.
Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values.
102 handbook, halfpage |yfs | (mS)
MGS313
-102 fs (deg)
handbook, halfpage
10
MGS314
|y fs|
yos (mS)
fs 10
bos -10 1
g os 1 10 -1 102 f (MHz) 103 10 -1 10 102 f (MHz) 103
VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C.
Fig.19 Forward transfer admittance and phase as a function of frequency; typical values.
Fig.20 Output admittance as a function of frequency; typical values.
1999 May 14
8
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1101; BF1101R; BF1101WR
handbook, full pagewidth
VAGC R1 10 k
C1 4.7 nF C3 4.7 nF
C2 RGEN 50 VI R2 50 4.7 nF RG1
DUT
L1 2.2 H C4 4.7 nF
RL 50
VGG
VDS
MGS315
Fig.21 Cross-modulation test set-up.
Table 1 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 2
Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C S11 MAGNITUDE (ratio) 0.987 0.985 0.976 0.963 0.949 0.933 0.916 0.897 0.877 0.856 0.832 ANGLE (deg) -4.1 -8.1 -16.1 -23.9 -31.6 -38.8 -45.7 -52.2 -58.4 -64.5 -70.3 S21 MAGNITUDE (ratio) 2.922 2.908 2.875 2.820 2.762 2.665 2.591 2.498 2.410 2.318 2.214 ANGLE (deg) 175.0 170.3 160.8 157.6 142.6 134.1 125.7 117.7 109.6 101.6 94.2 S12 MAGNITUDE (ratio) 0.001 0.001 0.003 0.004 0.005 0.005 0.005 0.006 0.005 0.006 0.006 ANGLE (deg) 87.6 86.1 83.3 80.4 78.2 77.8 78.9 81.8 89.1 97.1 110.4 S22 MAGNITUDE (ratio) 0.990 0.989 0.985 0.982 0.977 0.972 0.967 0.961 0.957 0.950 0.946 ANGLE (deg) -2.2 -4.3 -8.5 -12.6 -16.8 -20.8 -24.7 -28.5 -32.2 -35.8 -39.6
Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C f (MHz) 800 Fmin (dB) 1.5 opt (ratio) 0.715 (deg) 58.3 Rn () 37.85
1999 May 14
9
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
PACKAGE OUTLINES Plastic surface mounted package; 4 leads
BF1101; BF1101R; BF1101WR
SOT143B
D
B
E
A
X
y vMA HE
e bp wM B
4
3
Q
A
A1 c
1
b1 e1
2
Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.45 0.15 Q 0.55 0.45 v 0.2 w 0.1 y 0.1
OUTLINE VERSION SOT143B
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 97-02-28
1999 May 14
10
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1101; BF1101R; BF1101WR
Plastic surface mounted package; reverse pinning; 4 leads
SOT143R
D
B
E
A
X
y vMA HE
e bp wM B
3
4
Q
A
A1 c
2
b1 e1
1
Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.55 0.25 Q 0.45 0.25 v 0.2 w 0.1 y 0.1
OUTLINE VERSION SOT143R
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 97-03-10
1999 May 14
11
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1101; BF1101R; BF1101WR
Plastic surface mounted package; reverse pinning; 4 leads
SOT343R
D
B
E
A
X
y
HE e
vMA
3
4
Q
A A1 c
2
wM B bp e1 b1
1
Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.4 0.3 b1 0.7 0.5 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 1.15 HE 2.2 2.0 Lp 0.45 0.15 Q 0.23 0.13 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT343R
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 97-05-21
1999 May 14
12
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
DEFINITIONS Data Sheet Status Objective specification Preliminary specification Product specification Limiting values
BF1101; BF1101R; BF1101WR
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1999 May 14
13
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
NOTES
BF1101; BF1101R; BF1101WR
1999 May 14
14
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
NOTES
BF1101; BF1101R; BF1101WR
1999 May 14
15
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 64
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
125004/00/02/pp16
Date of release: 1999 May 14
Document order number:
9397 750 05993

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